Course Summary
This course equips semiconductor engineers with the co-design frameworks, interface protocols, and verification strategies required to architect production-grade chiplet-based heterogeneous systems. From UCIe die-to-die signaling to thermal-aware 3D stacking, every module targets real engineering trade-offs — not theory.
Learning Objectives
- Select and configure die-to-die interconnect protocols (UCIe, BoW, HBM PHY) against bandwidth density and power budget constraints
- Apply co-design rules across chiplet boundaries to prevent signal integrity, thermal, and mechanical failure modes in 2.5D/3D stacks
- Construct a verification closure plan covering pre-silicon emulation, post-bond electrical test, and known-good-die (KGD) yield qualification
- Evaluate packaging architectures — CoWoS, EMIB, SoIC, Foveros — against cost, performance, and supply chain risk criteria
- Integrate UCIe IP and validate functional correctness at the system level using a structured handshake and loopback test strategy
Course Summary
Cleanroom discipline is mostly behaviour, and the biggest contamination source is the person in the room. This course covers gowning, material transfer and conduct to the standard a classified environment requires.
Learning Objectives
- Describe cleanroom classifications and what they permit
- Gown and de-gown in the correct sequence
- Transfer materials without breaching control
- Follow conduct and movement rules inside a cleanroom
- Recognise and report a contamination event
Course Summary
What holds your circuit board together is more than just a line of shiny solder—it's the science beneath the surface. In this course, you'll uncover the critical role of the Intermetallic Compound (IMC) layer in solder joints and learn how microscopic details determine the reliability of every connection. Master the art of analyzing solder joint micrographs, optimize your reflow process, and apply industry standards to achieve robust, high-reliability assemblies. Designed for engineers and technicians who demand precision, this course equips you with the tools, standards, and know-how to prevent failures and ensure your products perform where it matters most.
Course Summary
This course builds operator-level mastery of IPC-A-610 and J-STD-001 solder inspection standards. You'll learn to classify product classes, identify acceptable versus defective joints, apply accept/reject criteria, and correctly flag and escalate defects — protecting product quality and safety on every assembly that leaves your line.
Learning Objectives
- Classify products by IPC-A-610 Class 1/2/3
- Identify acceptable solder joint visual criteria
- Recognize and name common solder defects
- Apply accept/reject/escalate decisions correctly
- Flag and escalate defects per protocol — never self-correct
Course Summary
Electrostatic discharge damages parts without leaving a mark, which is why it is so often missed. This course builds the habits that prevent it — how charge builds, why latent damage is the real cost, and what correct handling looks like at the bench.
Learning Objectives
- Explain how static charge builds and discharges
- Recognise catastrophic versus latent ESD damage
- Use wrist straps, mats and ESD-safe packaging correctly
- Work correctly inside an EPA
- Identify and report ESD control failures
Course Summary
This course covers the physics and math behind ESD failures, then walks through how to specify ionization, calculate RC decay, and select materials that hold up at real production speeds. By the end, you'll build a layered, system-level ESD strategy and defend it in an audit.
Learning Objectives
- Specify ionization and offset voltage requirements for automated EPAs.
- Calculate the RC decay time and compare it to the machine cycle speed.
- Select ESD-safe materials in the 10⁶–10⁹ Ω dissipative range.
- Build a layered, system-level ESD mitigation strategy.